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high speed adc usb fifo evaluation kit HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features buffer memory board for capturing digital data used with high speed adc evaluation boards to simplify evaluation 32 kb fifo depth at 133 msps (upgradable) measures performance with adc analyzer? real-time fft and time domain analysis analyzes snr, sinad, sfdr, and harmonics simple usb port interface (2.0) supporting adcs with serial port interfaces (spi?) on-board regulator circuit, no power supply required 6 v, 2 a switching power supply included compatible with windows? 98 (2nd ed.), windows 2000, windows me, and windows xp equipment needed analog signal source and antialiasing filter low jitter clock source high speed adc evaluation board and adc data sheet pc running windows 98 (2nd ed.), windows 2000, windows me, or windows xp latest version of adc analyzer usb 2.0 port recommended (usb 1.1-compatible) product description the high speed adc fifo evaluation kit includes the latest version of adc analyzer and a buffer memory board to capture blocks of digital data from the analog devices high speed analog-to-digital converter (adc) evaluation boards. the fifo board is connected to the pc through a usb port and is used with adc analyzer to quickly evaluate the performance of high speed adcs. users can view an fft for a specific analog input and encode rate to analyze snr, sinad, sfdr, and harmonic information . the evaluation kit is easy to set up. additional equipment needed includes an analog devices high speed adc evaluation board, a signal source, and a clock source. once the kit is connected and powered, the evaluation is enabled instantly on the pc. two versions of the fifo are available. the hsc-adc-evalb- dc is used with multichannel adcs and converters with demulti- plexed digital outputs. the HSC-ADC-EVALB-SC evaluation board is used with single-channel adcs. see table 1 to choose the fifo appropriate for your high speed adc evaluation board. functional block diagram clock input filtered analog input single or dual high-speed adc evaluation board 120-pin connector HSC-ADC-EVALB-SC or hsc-adc-evalb-dc clock circuit logic spi adc n n spi +3.0v reg ps chb fifo, 32k, 133mhz timing circuit cha fifo, 32k, 133mhz usb ctlr ps reg standard usb 2.0 05870-001 figure 1. product highlights 1. easy to set up. connect the included power supply and signal sources to the two evaluation boards. then connect to the pc and evaluate the performance instantly. 2. adisimadc?. adc analyzer supports virtual adc evaluation using adi proprietary behavioral modeling technology. this allows rapid comparison between multiple adcs, with or without hardware evaluation boards. for more information, see an-737 at www.analog.com/adisimadc . 3. usb port connection to pc. pc interface is a usb 2.0 connection (1.1-compatible) to the pc. a usb cable is provided in the kit. 4. 32 kb fifo. the fifo stores data from the adc for processing. a pin-compatible fifo family is used for easy upgrading. 5. up to 133 msps encode rate on each channel. single- channel adcs with encode rates up to 133 msps can be used with the fifo board. multichannel and demultiplexed output adcs can also be used with the fifo board with clock rates up to 266 msps. 6. supports adc with serial port interface or spi. some adcs include a feature set that can be changed via the spi. the fifo supports these spi-driven features through the existing usb connection to the computer without additional cabling needed.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 equipment needed ........................................................................... 1 product description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 fifo evaluation board easy start .................................................. 3 requirements ................................................................................ 3 easy start steps ............................................................................. 3 virtual evaluation board easy start with adisimadc ............ 4 requirements ................................................................................ 4 easy start steps ............................................................................. 4 fifo 4.1 data capture board features ......................................... 5 fifo 4.1 supported adc evaluation boards .......................... 6 theory of operation ........................................................................ 9 clocking description ................................................................... 9 spi description ............................................................................. 9 clocking with interleaved data ................................................ 10 connecting to the hsc-adc-fpga-4/-8 ............................. 10 connecting to the demux brd ............................................ 10 upgrading fifo memory ......................................................... 10 jumpers ............................................................................................ 11 default settings ........................................................................... 11 evaluation board ............................................................................ 13 power supplies ............................................................................ 13 connection and setup ............................................................... 13 fifo schematics and pcb layout ............................................... 14 schematics ................................................................................... 14 pcb layout ................................................................................. 21 bill of materials ............................................................................... 23 ordering information .................................................................... 25 ordering guide .......................................................................... 25 esd caution ................................................................................ 25 revision history 2/06revision 0: initial version
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 3 of 28 fifo evaluation board easy start requirements ? fifo evaluation board, adc analyzer, and usb cable ? high speed adc evaluation board and adc data sheet ? power supply for adc evaluation board ? analog signal source and appropriate filtering ? low jitter clock source applicable for specific adc evaluation, typically <1 ps rms ? pc running windows 98 (2nd ed.), windows 2000, windows me, or windows xp ? pc with a usb 2.0 port recommended (usb 1.1- compatible) easy start steps note: you need administrative rights for the windows operating systems during the entire easy start procedure. it is recommended to complete every step before reverting to a normal user mode. 1. install adc analyzer from the cd provided in the fifo evaluation kit or download the latest version on the web. for the latest updates to the software, check the analog devices website at www.analog.com/hsc-fifo . 2. connect the fifo evaluation board to the adc evaluation board. if an adapter is required, insert the adapter between the adc evaluation board and the fifo board. if using the HSC-ADC-EVALB-SC model, connect the evaluation board to the bottom two rows of the 120-pin connector, closest to the installed idt fifo chip. if using an adc with a spi interface, remove the two 4-pin corner keys so that the third row can be connected. 3. connect the provided usb cable to the fifo evaluation board and to an available usb port on the computer. 4. refer to table 5 for any jumper changes. most evaluation boards can be used with the default settings. 5. after verification, connect the appropriate power supplies to the adc evaluation boards. the fifo evaluation board is supplied with a wall mount switching power supply that provides a 6 v, 2 a maximum output. connect the supply end to the rated 100 ac to 240 ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at j301. refer to the instructions included in the adc data sheet for more information about the adc evaluation boards power supply and other requirements. 6. once the cable is connected to both the computer and the fifo board, and power is supplied, the usb drivers start to install. to complete the total installation of the fifo drivers, you need to complete the new hardware sequence two times. the first found new hardware wizard opens with the text message this wizard helps you install software forpre-fifo 4.1 . click the recommended install, and go to the next screen. a hardware installation warning window should then be displayed. click continue anyway . the next window that opens should finish the pre- fifo 4.1 installation. click finish . your computer should go through a second found new hardware wizard , and the text message, this wizard helps you install software foranalog devices fifo 4.1 , should be displayed. continue as you did in the previous installation and click continue anyway . then click finish on the next two windows. this completes the installation. 7. (optional) verify in the device manager that analog devices, fifo4.1 is listed under the usb hardware. 8. apply power to the evaluation board and check the voltage levels at the board level. 9. connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. make sure the evaluation boards are powered on before connecting the analog input and clock. 10. start adc analyzer. 11. choose an existing configuration file for the adc evaluation board or create one. 12. click time data in adc analyzer (left-most button under the menus). a reconstruction of the analog input is displayed. if the expected signal does not appear, or if there is only a flat red line, refer to the adc analyzer data sheet at www.analog.com/hsc-fifo for more information.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 4 of 28 virtual evaluation board easy start with adisimadc requirements requirements include ? completed installation of adc analyzer, version 4.5.17 or later. ? adisimadc product model files for the desired converter. models are not installed with the software, but they can be downloaded from the adisimadc virtual evaluation board website at no charge. no hardware is required. however, if you wish to compare results of a real evaluation board and the model, you can switch easily between the two, as outlined in the following easy start steps section. easy start steps 1. to get adc model files, go to www.analog.com/adisimadc for the product of interest. download the product of interest to a local drive. the default location is c:\program files\adc_analyzer\models . 2. start adc analyzer (see the adc analyzer user manual ). 3. from the menu, click config > buffer > model as the buffer memory. in effect, the model functions in place of the adc and data capture hardware. 4. after selecting the model, click the model button (located next to the stop button) to select and configure which converter is to be modeled. a dialog box appears in the workspace, where you can select and configure the behavior of the model. 5. in the adc modeling dialog box, click the device tab and then click the (browse) button, adjacent to the dialog box. this opens a file browser and displays all of the models found in the default directory: c:\program files\adc_analyzer\models. if no model files are found, follow the on-screen directions or see step 1 to install available models. if you have saved the models somewhere other than the default location, use the browser to navigate to that location and select the file of interest. 6. from the menu, click config > fft . in the fft configuration dialog box, ensure that the encode frequency is set for a valid rate for the simulated device under test. if set too low or too high, the model does not run. 7. once a model has been selected, information about the model displays on the device tab of the adc modeling dialog box. after ensuring that you have selected the right model, click the input tab. this lets you configure the input to the model. click either sine wave or two tone for the input signal. 8. click time data (left-most button under the pull-down menus). a reconstruction of the analog input is displayed . the model can now be used just as a standard evaluation board would be. 9. the model supports additional features not found when testing a standard evaluation board. when using the modeling capabilities, it is possible to sweep either the analog amplitude or the analog frequency. for more information consult the adc analyzer user manual at www.analog.com/hsc-fifo .
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 5 of 28 fifo 4.1 data capture board features 6v switching power supply connection on board +3.3v regulator optional power connection usb connection to computer controller crystal clock = 24mhz, off during data capture reset switch when encode rate is interrupted optional serial port interface connector open solder mask on all data and clock lines for easy probing idt72v283 32k ? 16-bit 133mhz fifo 120-connector (parallel cmos inputs) timing adjustment jumpers idt72v283 32k ? 16-bit 133mhz fifo 05870-002 figure 2. fifo components (top view)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 6 of 28 120-connector (parallel cmos inputs) timing adjustment jumpers driver circuit for serial port interface (spi) lines optional serial port interface (spi) connector cypress fx2 high speed usb 2.0 controller eprom to load usb firmware 05870-003 figure 3. fifo components (bottom view) fifo 4.1 supported adc evaluation boards the evaluation boards in table 1 can be used with the high speed adc fifo evaluation kit. some evaluation boards require an adapter between the adc evaluation board connector and the fifo connector . if an adapter is needed, send an email to highspeed.converters@analog.com with the part number of the adapter and a mailing address. table 1. hsc-adc-evalb-dc - and HSC-ADC-EVALB-SC-compatible evaluation boards 1 evaluation board model description of adc fifo board version comments ad6644st/pcb 14-bit, 65 msps adc sc ad6645-80/pcb 14-bit, 80 msps adc sc ad6645-105/pcb 14-bit, 105 msps adc sc ad9051/pcb 10-bit, 60 msps adc sc requires ad9051ffa ad9200ssop-eval 10-bit, 20 msps adc sc requires ad922xffa ad9200tqfp-eval 10-bit, 20 msps adc sc requires ad922xffa ad9201-eval dual 10-bit, 20 msps adc 1 sc requires ad922xffa ad9203-eb 10-bit, 40 msps adc sc requires ad922xffa ad9212-65eb 1 octal 10-bit, 65 msps adc dc requires hsc-adc-fpga-8 ad9215bcp-65eb 10-bit, 65 msps adc sc ad9215bcp-80eb 10-bit, 80 msps adc sc ad9215bcp-105eb 10-bit, 105 msps adc sc ad9215bru-65eb 10-bit, 65 msps adc sc ad9215bru-80eb 10-bit, 80 msps adc sc ad9215bru-105eb 10-bit, 105 msps adc sc ad9216-80pcb dual 10-bit, 80 msps adc dc ad9216-105pcb dual 10-bit, 105 msps adc dc
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 7 of 28 evaluation board model description of adc fifo board version comments ad9218-105pcb 10-bit, 105 msps adc dc ad9218-65pcb 10-bit, 65 msps adc dc ad9219-65eb 1 quad 10-bit, 65 msps adc dc requires hsc-adc-fpga-4/-8 ad9220-eb 12-bit, 10 msps adc sc requires ad922xffa ad9222-65eb 1 octal 12-bit, 65 msps adc dc requires hsc-adc-fpga-8 ad9226-eb 12-bit, 65 msps adc sc requires ad922xffa ad9226qfp-eb 12-bit, 65 msps adc sc requires ad922xffa ad9228-65eb 1 quad 12-bit, 65 msps adc dc requires hsc-adc-fpga-4/-8 ad9229-65eb 1 quad 12-bit, 65 msps adc dc requires hsc-adc-fpga-4/-8 ad9233-80eb 12-bit, 80msps adc sc ad9233-105eb 12-bit, 105msps adc sc ad9233-125eb 12-bit, 125msps adc sc ad9234-eb 12-bit, 150msps adc sc ad9235bcp-20eb 12-bit, 20 msps adc sc ad9235bcp-40eb 12-bit, 40 msps adc sc ad9235bcp-65eb 12-bit, 65 msps adc sc ad9235-20pcb 12-bit, 20 msps adc sc ad9235-40pcb 12-bit, 40 msps adc sc ad9235-65pcb 12-bit, 65 msps adc sc ad9236bru-80eb 12-bit, 80 msps adc sc ad9236bcp-80eb 12-bit, 80 msps adc sc ad9237bcp-20eb 12-bit, 20 msps adc sc ad9237bcp-40eb 12-bit, 40 msps adc sc ad9237bcp-65eb 12-bit, 65 msps adc sc ad9238bst-20pcb dual 12-bit, 20 msps adc dc ad9238bst-40pcb dual 12-bit, 40 msps adc dc ad9238bst-65pcb dual 12-bit, 65 msps adc dc ad9238bcp-20eb dual 12-bit, 20 msps adc dc ad9238bcp-40eb dual 12-bit, 40 msps adc dc ad9238bcp-65eb dual 12-bit, 65 msps adc dc ad9240-eb 14-bit, 40 msps adc sc requires ad922xffa ad9241-eb 14-bit, 1.25 msps adc sc requires ad922xffa ad9243-eb 14-bit, 3 msps adc sc requires ad922xffa ad9244-40pcb 14-bit, 40 msps adc sc ad9244-65pcb 14-bit, 65 msps adc sc ad9245bcp-20eb 14-bit, 20 msps adc sc ad9245bcp-40eb 14-bit, 40 msps adc sc ad9245bcp-65eb 14-bit, 65 msps adc sc ad9245bcp-80eb 14-bit, 80 msps adc sc ad9246-80eb 14-bit, 80 msps adc sc ad9246-105eb 14-bit, 105 msps adc sc ad9246-125eb 14-bit, 125 msps adc sc ad9248bst-65eb dual 14-bit, 65 msps adc dc ad9248bcp-20eb dual 14-bit, 20 msps adc dc ad9248bcp-40eb dual 14-bit, 40 msps adc dc ad9248bcp-65eb dual 14-bit, 65 msps adc dc ad9259-50eb 1 quad 14-bit, 50 msps adc dc requires hsc-adc-fpga-4/-8 ad9260-eb 16-bit, 2.5 msps adc sc requires ad922xffa ad9280-eb 8-bit, 32 msps adc sc requires ad922xffa ad9281-eb dual 8-bit, 28 msps adc sc requires ad922xffa ad9283/pcb 8-bit, 100 msps adc sc requires ad9283ffa ad9287-100eb 1 quad 8-bit, 100 msps adc dc requires hsc-adc-fpga-4/-8 ad9289-65eb 1 quad 8-bit, 65 msps adc dc requires hsc-adc-fpga-9289 ad9411/pcb 10-bit, 200 msps adc dc requires demux brd
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 8 of 28 evaluation board model description of adc fifo board version comments ad9430-cmos/pcb 12-bit, 210 msps adc dc ad9430-lvds/pcb 2 12-bit, 210 msps adc dc requires demux brd ad9432/pcb 12-bit, 105 msps adc sc ad9433/pcb 12-bit, 125 msps adc sc ad9444-cmos/pcb 14 bit, 80 msps adc sc ad9444-lvds/pcb 14 bit, 80 msps adc sc ad9445-if-lvds/pcb 14-bit, 125 msps adc sc ad9445-bb-lvds/pcb 14-bit, 125 msps adc sc ad9446-80lvds/pcb 16-bit, 80 msps adc sc ad9446-100lvds/pcb 16-bit, 100 msps adc sc ad9460-80eb-if 16-bit, 80 msps adc sc ad9460-80eb-bb 16-bit, 80 msps adc sc ad9460-105eb-if 16-bit, 105 msps adc sc ad9460-105eb-bb 16-bit, 105 msps adc sc ad9461-130eb-if 16-bit, 130 msps adc sc ad9461-130eb-bb 16-bit, 130 msps adc sc ad9480-lvds/pcb 2 8-bit, 250 msps adc dc requires demux brd ad9481-pcb 8-bit, 250 msps adc dc ad10200/pcb dual 12-bit, 105 msps adc dc requires gs09066 ad10201/pcb dual 12-bit, 105 msps adc dc requires gs09066 ad10226/pcb dual 12-bit, 125 msps adc dc requires gs09066 ad10265/pcb dual 12-bit, 65 msps adc dc requires gs09066 ad10465/pcb dual 14-bit, 65 msps adc dc requires gs09066 ad10677/pcb 16-bit, 65 msps adc sc requires gs09066 ad10678/pcb 16-bit, 80 msps adc sc requires gs09066 ad15252/pcb 12-bit, dual 65 msps adc dc ad15452/pcb 12-bit, quad 65 msps adc dc requires hsc-adc-fpga-4/-8 1 the high speed adc fifo evalua tion kit can be used to eval uate two channels at a time. 2 if a demux brd is needed, send an e mail to highspeed.converters@analog.com.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 9 of 28 theory of operation the fifo evaluation board can be divided into several circuits, each of which plays an important part in acquiring digital data from the adc and allows the pc to upload and process that data. the evaluation kit is based around the idt72v283 fifo chip from integrated device technology, inc (idt). the system can acquire digital data at speeds up to 133 msps and data record lengths up to 32 kb using the HSC-ADC-EVALB-SC fifo evaluation kit. the hsc-adc-evalb-dc, which has two fifo chips, is available to evaluate multichannel adcs or demultiplexed data from adcs sampling faster than 133 msps. a usb 2.0 microcontroller communicating with adc analyzer allows for easy interfacing to newer computers using the usb 2.0 (usb 1.1-compatible) interface. the process of filling the fifo chip or chips and reading the data back requires several steps. first, adc analyzer initiates the fifo chip fill process. the fifo chips are reset, using a master reset signal (mrs). the usb microcontroller is then suspended, which turns off the usb oscillator and ensures that it does not add noise to the adc input. after the fifo chips completely fill, the full flags from the fifo chips send a signal to the usb microcontroller to wake up the microcontroller from suspend. adc analyzer waits for approximately 30 ms and then begins the readback process. during the readback process, the acquisition of data from fifo 1 (u201) or fifo 2 (u101) is controlled via signal oea and signal oeb. because the data outputs of both fifo chips drive the same 16-bit data bus, the usb microcontroller controls the oea and oeb signals to read data from the correct fifo chip. from an application standpoint, adc analyzer sends commands to the usb microcontroller to initiate a read from the correct fifo chip, or from both fifo chips in dual or demultiplexed mode. clocking description each channel of the buffer memory requires a clock signal to capture data. these clock signals are normally provided by the adc evaluation board and are passed along with the data through connector j104 (pin 37 for both channel a and channel b). if only a single clock is passed for both channels, they can be connected together by jumper j303. jumpers j304 and j305 at the output of the lvds receiver allow the output clock to be inverted by the lvds receiver. by default, the clock outputs are inverted by the lvds receiver. the single-ended clock signal from each data channel is buffered and converted to a differential cmos signal by two gates of a low voltage differential signal (lvds) receiver, u301. this allows the clock source for each channel to be cmos, ttl, or ecl. the clock signals are ac-coupled by 0.1 f capacitors. potentiometer r312 and potentiometer r315 allow for fine tuning the threshold of the lvds gates. in applications where fine-tuning the threshold is critical, these potentiometers can be replaced with a higher resistance value to increase the adjustment range. resistors r301, r302, r303, r304, r311, r313, r314, and r316 set the static input to each of the differential gates to a dc voltage of approximately 1.5 v. at assembly, solder jumper j310 to solder jumper j313 are set to bypass the potentiometer. for fine adjustment using the pot, the solder jumpers must be removed, and r312 and r315 must be populated. u302, an xor gate array, is included in the design to let users add gate delays to the fifo memory chip clock paths. they are not required under normal conditions and are bypassed at assembly by jumper j314 and jumper j315. jumper j306 and jumper j307 allow the clock signals to be inverted through an xor gate. in the default setting, the clocks are not inverted by the xor gate. the clock paths described above determine the wrt_clk1 and wrt_clk2 signals at each fifo memory chip (u101 and u201). the timing options above should let you choose a clock signal that meets the setup and hold time requirements to capture valid data. a clock generator can be applied directly to s1 and/or s3. this clock generator should be the same unit that provides the clock for the adc. these clock paths are ac-coupled, so that a sine wave generator can be used. dc bias can be adjusted by r301/r302 and r303/r304. the ds90lv048a differential line receiver is used to square the clock signal levels applied externally to the fifo evaluation board. the output of this clock receiver can either directly drive the write clock of the idt72v283 fifo(s), or first pass through the xor gate timing circuitry described above. spi description the cypress ic (u502) supports the hsc spi standard to allow programming of adcs that have spi-accessible register maps. u102 is a buffer that drives the 4-wire spi (sclk, sdi, sdo, csb 1 ) through the 120-pin connector (j104) on the third or top row. j502 is an auxiliary spi connector to monitor the spi signals connected directly to the cypress ic. for more information on this and other functions, consult the user manual titled interfacing to high speed adcs via spi at www.analog.com/hsc-fifo . 1 note that csb1 is the default csb line used.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 10 of 28 the spi interface designed on the cypress ic can communicate with up to five different spi-enabled devices. the clk and data lines are common to all spi devices. the correct device is chosen to communicate by using one of the five active low chip select pins. this functionality is controlled by selecting a spi channel in the software. clocking with interleaved data adcs with very high data rates can exceed the capability of a single buffer memory channel (~133 msps). these converters often demultiplex the data into two channels to reduce the rate required to capture the data. in these applications, adc analyzer must interleave the data from both channels to process it as a single channel. the user can configure the software to process the first sample from channel a, the second from channel b, and so on, or vice versa. the synchronization circuit included in the buffer memory forces a small delay between the write enable signals (wena and wenb) to the fifo memory chips (pin 1, u101, and u201), ensuring that the data is captured in one fifo before the other. jumper j401 and jumper j402 determine which fifo receives wena and which fifo receives wenb. connecting to the hsc-adc-fpga-4/-8 adcs that have serial lvds outputs require another board that is connected between the adc evaluation board and the fifo data capture card. this board converts the serial data into parallel cmos so that the fifo data capture card can accept the data. for more detailed information on this board, refer to the hsc-adc-fpga datasheet at www.analog.com/hsc-fifo . connecting to the demux brd adcs that have parallel lvds outputs require another board that is connected between the adc evaluation board and the fifo data capture card. this board converts parallel lvds to parallel cmos, using both channels of the fifo data capture card. for more detailed information on this board, send an email to highspeed.converters@analog.com upgrading fifo memory the fifo evaluation board includes one or two 32 kb fifos that are capable of 133 mhz clock signals, depending on the model number. pin-compatible fifo upgrades are available from idt. see table 2 for the idt part number matrix. table 2. idt part number matrix part number fifo depth fifo speed idt72v283-l7-5pf (default ) 32 kb 133 mhz idt72v293-l7-5pf 64 kb 133 mhz idt72v2103-l7-5pf 132 kb 133 mhz idt72v2113-l7-5pf 256 kb 133 mhz idt72v283-l6pf 32 kb 166 mhz idt72v293-l6pf 64 kb 166 mhz idt72v2103-l6pf 132 kb 166 mhz idt72v2113-l6pf 256 kb 166 mhz for more information, visit www.idt.com.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 11 of 28 jumpers use the legends in table 3 and table 4 to configure the jumpers. on the fifo evaluation board, channel a is associated with the bottom idt fifo chip, and channel b is associated with the top idt fifo chip (closest to the analog devices logo). table 3. jumper legend position description in jumper in place (2-pin header). out jumper removed (2-pin header). position 1 or position 3 denotes the position of a 3-pin header. position 1 is marked on the board. table 4. solder jumper legend position description in solder pads should be connected with 0 resistor. out solder pads should not be connected with 0 resistor. default settings table 5 lists the default settings for each model of the fifo evaluation kit. the single channel (sc) model is configured to work with a single channel adc using the bottom fifo, u201. the dual channel (dc) model is configured to work with demultiplexed adcs (such as the ad9430). dual channel adc settings are shown in a separate column, as are settings for the opposite (top) fifo, u101 for a single channel adc. to align the timing properly, some evaluation boards require modifications to these settings. refer to the clocking description section in the theory of operation section for more information. another useful way to configure the jumper settings easily for various configurations is to consult adc analyzer under help > about hsc_adc_evalb , and click set up default jumper wizard . then click the configuration setting that applies to the application of interest. a picture of the fifo board is displayed for that application with a visual of the correct jumper settings already in place. table 5. jumper configurations jumper # single channel settings, default (bottom) demultiplexed settings dual-channel settings single-channel settings (top) 1 description j303 in out out in position 2 to posi tion 4, ties write clocks together j304 in in in in position 1 to position 2, pos3: invert clock out of ds90 (u301) j305 in in in in position 2 to position 3, pos3: invert clock out of ds90 (u301) j306 out out out out no invert to encode clock from xor (u302), 0 resistor j307 out out out out no invert to encode clock from xor (u302), 0 resistor j310 to j313 in in in in all solder jumpers are shorted with 0 resistors (bypass level shifting to input of ds90) j314 in in in in position 1 to position 2, one xor gate timing delay for top fifo (u101) j315 in in in in position 1 to position 2, one xor gate timing delay for bottom fifo (u201) j316 in in in in power connected using switching power supply j401 in in in in controls if top fifo (u101) gets write enable before or after bottom fifo, 0 resistor j402 out out out out controls if top fifo (u101) gets write enable before or after bottom fifo, 0 resistor j403 out out out out controls if bottom fifo (u201) gets a write enable before or after the top fifo, 0 resistor j404 in in in in controls if bottom fifo (u201) gets a write enable before or after the top fifo, 0 resistor j405 out in out out when in, wrt_clk1 is used to create write enable signal for fifos, 0 resistor (significant only for interleave mode)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 12 of 28 jumper # single channel settings, default (bottom) demultiplexed settings dual-channel settings single-channel settings (top) 1 description j406 in in in in wrt_clk2 is used to create write enable signal for fifos, 0 resistor (significant only for interleave mode) j503 in in in in connect enable empty flag of top fifo (u101) to usb mcu, 0 resistor j504 out out out out n/a j505 in in in in connect enable full flag of top fifo (u101) to usb mcu, 0 resistor j506 out out out out n/a j602 out out out out n/a j603 in in in in n/a 1 some jumpers can be a 0 resistor instead of a physical jumpe r. this is shown in table 5 in the jumper description column.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 13 of 28 evaluation board the fifo provides all of the support circuitry required to accept two channels of an adcs digital parallel cmos outputs. each of the various functions and configurations can be selected by proper connection of various jumpers (see tabl e 5 ). when using this in conjunction with an adc evaluation board, it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 5 to figure 15 for complete schematics and layout plots. power supplies the fifo board is supplied with a wall mount switching power supply that provides a 6 v, 2 a maximum output. connect the supply to the rated 100 ac to 240 ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at j301. on the pc board, the 6 v supply is then fused and conditioned before connecting to the low dropout 3.3 v linear regulator that supplies the proper bias to the entire board. when operating the evaluation board in a non-default condition, j316 can be removed to disconnect the switching power supply. this enables the user to bias the board independently. use p302 to connect an independent supply to the board. a 3.3 v supply is needed with at least a 1 a current capability. connection and setup the fifo board has a 120-pin (40-pin, triple row) connector that accepts two 16-bit channels of parallel cmos inputs (see figure 6 ). for those adc evaluation boards that have only an 80-pin (40-pin, double row) connector, it is pertinent for the lower two rows of the fifos triple row connector to be connected in order for the data to pass to either fifo channel correctly. the top or third row is used to pass spi signals across to the adjacent adc evaluation board that supports this feature. rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, smhu, 2v p-p signal synthesizer band-pass filter usb connection 05870-004 hsc-adc-evalb-dc fifo data capture board pc running adc analyzer ?+ 3.3v gnd vcc 6v dc 2a max wall outle t 100v to 240v ac 47hz to 63hz chb parallel cmos outputs evaluation board chb parallel cmos outputs xfmr input clk switching power supply spi spi spi figure 4. example setup using quad adc evaluation board and fifo data capture board
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 14 of 28 fifo schematics and pcb layout schematics 0 5870-005 vcc c101 0.1f c102 0.1f c103 0.1f c104 0.1f c105 0.1f c106 0.1f c107 0.1f c108 0.1f c109 0.1f ff/ir ld fwft/si paf ow fsel0 hf fsel1 be ip pae pfm ef/or rm rclk ren q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 oe rt d5 d4 d3 d2 d1 d0 q0 q1 q2 q3 q4 q5 q6 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 iw sen wen prs wclk mrs dnc vcc dnc gnd vcc gnd vcc vcc gnd gnd vcc gnd gnd vcc vcc gnd gnd gnd vcc gnd 14 20 23 3 30 33 36 39 4 44 46 48 5 51 54 55 58 67 7 9 29 28 17 16 15 13 12 11 10 8 27 26 25 24 22 21 19 18 64 75 72 70 76 68 6 77 73 65 31 32 45 47 49 50 52 53 56 57 34 35 37 38 40 41 42 43 62 63 80 69 71 78 59 66 74 79 61 60 2 1 u101 idt72v283 tqfp80 top fifo channel b q9 e102 e101 oe1 ren1 ef1_tf ff1_tf wen1 d1_16 d1_17 vcc rclk q0 q1 q2 q3 q4 q5 q6 q7 q8 q10 q11 q13 q14 q15 q16 q17 mrs wrt_clk1 q12 populate with pin socket d1_1 d1_0 d1_3 d1_2 d1_5 d1_4 d1_7 d1_6 d1_15 d1_14 d1_13 d1_12 d1_11 d1_10 d1_9 d1_8 r101 0 ? r102 10k ? pc2 a llow fx2 to control fifo?s output width pc2: tristated, normal 16-bit data path pc2: driven high, 9-bit output allows reading 18 bits in two reads. r108 dnp r109 dnp vcc wrt_clk1 figure 5. pcb schematic
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 15 of 28 c8 c1 c2 c3 c4 c5 c6 c7 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 j104 c28 c21 c22 c23 c24 c25 c26 c27 c29 c30 c31 c32 c33 c34 c35 c36 c37 c38 c39 c40 22 b8 b1 b2 b3 b4 b5 b6 b7 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 j104 b28 b21 b22 b23 b24 b25 b26 b27 b29 b30 b31 b32 b33 b34 b35 b36 b37 b38 b39 b40 ctrl_c ctrl_c ctrl_a d2_17 d2_16 ctrl_a d2_17 d2_16 d1_17 d1_16 d1_17 d1_16 a8 a1 a2 a3 a4 a5 a6 a7 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 j104 a28 a21 a22 a23 a24 a25 a26 a27 a29 a30 a31 a32 a33 a34 a35 a36 a37 a38 a39 a40 ctrl_d ctrl_d ctrl_b ctrl_b dut_clk2 d1_15 d1_14 d1_13 d1_12 d1_11 d1_10 d1_9 d1_8 d1_7 d1_6 d1_5 d1_4 d1_3 d1_2 d1_1 d1_0 d2_0 d2_0 d2_1 d2_1 d2_2 d2_2 d2_3 d2_3 d2_4 d2_4 d2_5 d2_5 d2_6 d2_6 d2_7 d2_7 d2_8 d2_8 d2_9 d2_9 d2_10 d2_10 d2_11 d2_11 d2_12 d2_12 d2_13 d2_13 d2_14 d2_14 d2_15 d2_15 d1_2 d1_3 d1_4 d1_5 d1_6 d1_7 d1_8 d1_9 d1_10 d1_11 d1_12 d1_13 d1_14 d1_15 d1_0 d1_1 dut_clk1 clkb msb lsb clka msb lsb chb cha test points placement of header key here placement of header key here test points sdo 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rz101 19 18 17 16 15 14 13 12 11 10 20 vcc y0 y1 y2 y3 y4 y5 y6 y7 a0 a1 a2 a3 a4 a5 a6 a7 74vhc541mtc gnd u102 oe2 vcc oe 1 2 3 4 5 6 7 8 9 csb1 csb2 sclk csb3 csb4 sdi r104 10k? r103 10k? all spi labels are with respect to the dut. 05870-006 cmos inputs figure 6. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 16 of 28 05870-007 vcc c201 0.1f c202 0.1f c203 0.1f c204 0.1f c205 0.1f c206 0.1f c207 0.1f c208 0.1f ff/ir ld fwft/si paf ow fsel0 hf fsel1 be ip pae pfm ef/or rm rclk ren q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 oe rt d5 d4 d3 d2 d1 d0 q0 q1 q2 q3 q4 q5 q6 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 iw sen wen prs wclk mrs dnc vcc dnc gnd vcc gnd vcc vcc gnd gnd vcc gnd gnd vcc vcc gnd gnd gnd vcc gnd 14 20 23 3 30 33 36 39 4 44 46 48 5 51 54 55 58 67 7 9 29 28 17 16 15 13 12 11 10 8 27 26 25 24 22 21 19 18 64 75 72 70 76 68 6 77 73 65 31 32 45 47 49 50 52 53 56 57 34 35 37 38 40 41 42 43 62 63 80 69 71 78 59 66 74 79 61 60 2 1 u201 idt72v283 tqfp80 bottom fifo channel a q9 e202 e201 oe2 ren2 ef2 ff2 wen2 d2_16 d2_17 vcc rclk q0 q1 q2 q3 q4 q5 q6 q7 q8 q10 q11 q13 q14 q15 q16 q17 mrs wrt_clk2 q12 popul a te with pin socket d2_1 d2_0 d2_3 d2_2 d2_5 d2_4 d2_7 d2_6 d2_15 d2_14 d2_13 d2_12 d2_11 d2_10 d2_9 d2_8 r201 0 ? r202 10k ? pc3 r203 dnp r204 dnp vcc wrt_clk2 figure 7. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 17 of 28 rin1+ 2 gnd 12 u301 en 6 vcc 13 rout2 14 rout1 15 rout3 11 rout4 10 rin1? 1 rin2+ 3 rin2? 4 rin3+ 6 rin3? 5 rin4+ 7 rin4? 8 ds90lv048a c305 0.1f vcc 1 3 j304 j305 3 1 c306 0.1f j306 r309 1k ? j307 r310 1k ? 1 2 3 u302 74vcx86 10 9 8 u302 74vcx86 vcc 12 13 11 u302 74vcx86 3 j315 1 wrt_clk2 5 4 6 u302 74vcx86 3 j314 1 wrt_clk1 e305 e306 en 9 j312 j313 r316 331? r315 dnp r314 331? c311 0.1f vcc j303 1 3 2 4 r301 331 ? r303 331? r304 331? vcc vcc top fifo dut_clk1 c302 0.1f bottom fifo dut_clk2 c303 0.1f e301 e302 populate with pin socket invert clock 1 invert clock 2 dnp dnp invert clock 1 invert clock 2 set 0, 1, or 2 xo r gate delays controls top fifo set 0, 1, or 2 xo r gate delays controls bottom fifo remove jumper for dual channel configuration r302 331 ? for coherent sampling remove r301-r304 and short c302 and c303 place jumpers between pads on top side j310 j311 r313 331? r312 dnp r311 331? c310 0.1f vcc top fifo bottom fifo 1 10 11 12 13 14 15 16 17 18 19 2 20 34 56 78 9 j308 dnp wens wrt_clk2 wrt_clk1 rclk ef2 ff2 ff1_f ef1_f oe1 oe2 ren2 ren1 mrs vcc aux clock signal monitor connector 12 j302 dnp vcc + c307 10f + c309 10f c308 0.1f optional power input header r317 499 ? cr303 12 j316 vo vi vo adj 4 2 1 3 c313 1f c312 1f vr301 adp3339akc-3.3 1 3 2 j301 pj-102a power supply input 6v, 2a max 2.2a + c301 10f cr301 s2a 12 43 t103 f301 cr302 sk33msct 0 5870-008 figure 8. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 18 of 28 1d0 2d0 4clk0 5clk0 d clk r q q s r0 19 s0 18 q0 17 q0 16 6clk 7clk d clk r q q s q1 15 q1 14 s1 13 r1 12 gnd 11 vcc 10 vbb 3 u402 4 3 6 u403 mc100ept23 7 2 1 u401 mc100ept22 1 2 7 u403 mc100ept23 wen1 wen2 r413 49.9 ? r414 49.9 ? r415 40.2 ? r407 49.9 ? r408 49.9 ? r409 40.2 ? 8d1 9d1 r410 49.9 ? r411 49.9 ? r412 40.2 ? r404 49.9 ? r405 49.9 ? r406 40.2 ? r403 dnp r402 dnp r401 20k ? vcc vcc c401 dnp wens 4 6 wrt_clk1 wrt_clk2 3 u401 mc100ept22 vcc c402 0.1f c403 0.1f c404 0.1f c405 0.1f j401 j402 dnp j403 j404 dnp j405 j406 dnp controls top fifo controls bottom fifo 05870-009 mc100ep29 figure 9. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 19 of 28 vcc c506 0.1f c515 0.1f c514 0.1f c513 0.1f c512 0.1f c5 11 0.1f c510 0.1f c509 0.1f c508 0.1f c507 0.1f c516 0.1f c517 0.1f a0 a1 sc l vss a2 vcc wp sda agnd gnd cs wr rd psen oe sd a sc l ea bkpt rese rved ifclk reset *wakeu p txd0 rxd0 txd1 rxd1 d5 d6 d7 ctl0*flag a ctl1/*flagb ctl2/*flagc ctl3 ctl4 ctl5 int4 t2 t1 t0 d0 d1 d2 d3 d4 nc3 nc2 nc1 pe7/gpi fadr8 pe6/t2ex pe5/int6 pe4/rxd1out pe3/rxd0out pe2/t2out pe1/t1out pe0/t0out pa7/*flag/slcs pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1 pa0/int0 avcc dvcc pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 pd7/fd15 pd6/fd14 pd5/fd13 pd4/fd12 pd3/fd 11 pd2/fd10 pd1/fd9 pd0/fd8 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 dminus dplus rdy5 rdy4 rdy3 rdy2 rdy0/*slrd xtalin xtalout clkout int5 13 3 42 41 40 39 38 37 36 35 34 33 32 99 101 50 51 52 53 86 87 88 69 70 71 66 67 98 28 31 30 29 59 60 61 62 63 16 15 14 115 114 113 112 111 110 109 108 79 78 77 76 75 74 73 72 92 91 90 89 85 84 83 82 10 2 57 56 55 54 47 46 45 44 124 123 122 121 105 104 103 102 25 24 23 22 21 128 127 126 120 119 118 117 97 96 95 94 19 18 9 8 7 6 5 4 12 11 1 106 cr501 1 2 y501 24mhz q16 oe1 oe2 ctrl_ a ctrl_b ctrl_c ctrl_d 1 2 5 6 4 3 7 8 u503 1 42 3 j501 cr502 vcc vcc ff2 ef2 q17 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ff_usb vcc usb_vbus e502 vcc rclk vcc cy7c68013_128axc u502 r504 24.9 ? r502 100k ? r505 24.9 ? r506 24.9 ? r507 24.9 ? r520 24.9 ? r525 24.9 ? r526 24.9 ? r510 24.9 ? r509 10k ? r508 10k ? r5 11 24.9 ? r512 24.9 ? r513 24.9 ? r514 24.9 ? r516 2k ? r517 2k ? r515 24.9 ? mrs wens ren1 renext ren2 r503 499 ? c504 12pf c505 12pf c503 0.1f c501 1f s501 = reset usb controller + pc2 pc3 sclk sdi csb1 csb2 csb3 csb4 csb5 sdo 1 2 3 4 s501 12 l501 e503 e504 e505 6 vcc r524 0 ? r523 2k? u505 q d clk q vcc gnd pre clr vcc 2 1 5 8 4 7 6 3 u504 mrs vcc 3 4 u505 1 2 14 7 u505 ff2 5 vcc vcc ff1_tf r522 332 ? r521 332 ? from top fifo from bot tom fifo r519 10k ? r518 10k ? 1 2 3 4 5 +v gnd ff_usb vcc u501 ff2 from top fifo from bot tom fifo j506 j505 dn p ff1_bhb ff1_tf j504 j503 dn p ef1_bhb ef1_tf j502 dn p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 05870-010 usb connection interleave_firstword rdy1/*slwr interle av e _ f i r s t w o r d contro l fifo output width pc0/gpi fadr0 pc1/gpi fadr1 pc2/gpi fadr2 pc3/gpi fadr3 pc5/gpi fadr5 pc6/gpi fadr6 pc7/gpi fadr7 pc4/gpi fadr4 all spi labelsare with respect to the dut vcc;17,26,43,48,64,68,81,100,107 gnd;20;27;49;58;65;80;93; 116;125 aux spi port connection ren2m ground test points c502 2.2f figure 10. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 20 of 28 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 rz602 dc15 dc14 dc13 dc12 dc10 dc9 dc8 dc11 d1_11 d1_8 d1_9 d1_10 d1_12 d1_13 d1_14 d1_15 d1_7 d1_6 d1_5 d1_4 d1_2 d1_1 d1_0 d1_3 dc3 dc0 dc1 dc2 dc4 dc5 dc6 dc7 9 8 7 6 5 4 3 2 16 15 14 13 12 11 10 1 rz601 dc16 d1_16 r603 0 ? dc17 d1_17 r604 0 ? 74lcx574 clock d0 d1 d2 d3 d4 d6 d7 gnd q0 q1 q2 q3 q4 q5 q6 q7 vcc out_en d5 7 1 20 12 13 14 15 16 17 18 19 10 9 8 6 5 4 3 2 11 u601 9 8 7 6 5 4 3 2 16 15 14 13 12 11 10 1 rz605 q4 q3 q0 q1 q2 q5 q6 q7 vcc ql0 ql1 ql2 ql3 ql4 ql5 ql6 ql7 renext v cc c601 0.1f ql1 ql2 ql5 ql6 ql7 ql4 ql0 9 8 7 68 67 66 65 64 63 62 61 60 6 59 58 57 56 55 54 53 52 51 50 5 49 48 47 46 45 44 43 42 41 40 4 39 38 37 36 35 34 33 32 31 30 3 29 28 27 26 25 24 23 22 21 20 2 19 18 17 16 15 14 13 12 11 10 1 j601 dc9 dc1 dc12 dc14 dc15 dc4 dc5 ql3 wrt_clk1 ef1_bhb ff1_bhb wen1 mrs rclk ren1 dc10 dc11 dc7 dc8 dc2 dc3 dc0 dc6 dc13 dc16 dc17 dnp j603 j602 dnp ren2m rclk j603: allows 2 meg buffer to read back data on each rclk edge. j602: allows 2 meg buffer to read back 1 data on every 3rd rclk edge. j602 is for backward compatability if needed. connections for 2m word external memory external memory overrides on board memories when plugged in. only a side data. 05870-011 figure 11. schematic (continued)
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 21 of 28 pcb layout 05870-012 figure 12. layer 1primary side 05870-013 figure 13. layer 2ground plane
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 22 of 28 05870-014 figure 14. layer 3power plane 05870-015 figure 15. layer 4secondary side
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 23 of 28 bill of materials table 6. HSC-ADC-EVALB-SC/hsc-a dc-evalb-dc bill of materials item qty reference designation device package description manufacturer mfg part number 1 42 c101 to c109, c201 to c208, c302, c303, c305, c306, c308, c310, c311, c402 to c405, c503, c506 to c517, c601 capacitor 402 ceramic, 0.1 f, 16 v, x5r, 10% panasonic ecj-0eb1c014k 2 3 c301, c307, c309 capacitor 6032-28 tantalum, 10 f, 16 v, 10% kemet t491c106k016as 3 2 c312, c313 capacitor 603 ceramic, 1 f, 10 v, x5r, 10% panasonic ecj-1vb1a105k 4 1 c501 capacitor 3216-18 tantalum, 1 f, 16 v, 20% panasonic ecs-t1cy105r 5 1 c502 capacitor 805 ceramic, 2.2 f, 25 v, x5r 10% panasonic ecj-2fb1e225k 6 2 c504, c505 capacitor 402 ceramic, 12 pf, npo, 50 v, 5% panasonic ecj-0ec1h120j 7 1 cr301 diode do-214aa schottky diode, 50 v, 2 a, smc micro commercial group s2a 8 1 cr302 diode do-214ab schottky diode, 30 v, 3 a, smc micro commercial group sk33msct 9 2 cr303, cr501 led 603 green, 4 v 5 m, candela panasonic lnj314g8tra 10 1 cr502 diode sod-123 switching, 75 v, 150 ma diodes, inc. 1n4148w-7 11 1 f301 fuse 1210 6.0 v, 2.2 a trip current resettable fuse tyco, raychem nanosmdc110f-2 12 1 j104 connector 120-pin, female, pc mount, right angle amp 650874 13 1 j301 connector 0.08, pcmt rapc722, power supply connector switchcraft sc1153 14 1 j303 connector 4-pin male, straight, 100 mil samtec tsw-1-10-08-gd 15 4 j304, j305, j314, j315 connector 3-pin male, straight, 100 mil samtec tws-103-08-g-s 16 8 j310 to j313, j401, j404, j406, j603 connector 603 2-pin solder jumper, 0 , 1/10 w, 5% panasonic erj-3gey0r00v 17 1 j316 connector 2-pin male, straight, 100 mil samtec tsw-1002-08-g-s 18 1 j501 connector 4-pin usb, pc mount, right angle, type b, female amp 787780-1 19 1 l501 ferrite bead 805 500 ma, 600 @ 100 mhz steward hz0805e601r-00 20 5 r101, r201, r524, r603, r604 resistor 402 0 , 1/16 w, 5% panasonic erj-2ge0r00x 21 8 r102 to r04, r202, r508, r509, r518, r4519 resistor 402 10 k, 1/16 w, 1% panasonic erj-2rkf1002x 22 10 r301 to r304, r311, r313, r314, r316, r521, r522 resistor 402 332 , 1/16 w, 1% panasonic erj-2rkf3320x 23 2 r309, r310 resistor 402 1 k, 1/16 w, 1% panasoni c erj-2rkf1002x 24 2 r317, r503 resistor 402 499 , 1/16 w, 1% panasoni c erj-2rkf1001x 25 1 r401 resistor 402 20 k, 1/16 w, 1% panasonic erj-2rkf4990x 26 8 r404, r405, r407, r408, r410, r411, r413, r414 resistor 402 49.9 , 1/16 w, 1% panasonic erj-2rkf2002x 27 4 r406, r409, r412, r415 resistor 402 40.2 , 1/16 w, 1% pana sonic erj-2rkf40r2x 28 1 r502 resistor 402 100 k, 1/16 w, 1% panasonic erj-2rkf1003x 29 13 r504, r506, r507, r510 to r515, r520, r525, r526 resistor 402 24.9 , 1/16 w, 1% panasonic erj-2rkf24r9x 30 3 r516, r517, r523 resistor 402 2 k, 1/16 w, 1% panaso nic erj-2rkf2001x 31 1 rz101 resistor resistor array, 22 , 1/4 w, 5% panasonic exb-2hv220jx 32 1 s501 switch momentary (normally open), 100 ge, 5 mm, spst panasonic evq-plda15
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 24 of 28 item qty reference designation device package description manufacturer mfg part number 33 1 t301 choke 2020 10 h, 5 a, 50 v, 190 @ 100 mhz murata dlw5bsn191sq2l 34 1 2 u101, u201 ic tqfp80 3.3 v, idt72v283l7-5pf idt idt72v283l7-5pf 35 1 u102 ic soic20 74vhc541, octal buffer/line driver, three-state fairchild 74vhc541m 36 1 u301 ic soic16 ds90lv048a national semiconductor ds90lv048a 37 1 u302 ic soic14 74vcx86 fairchild 74vcx86 38 1 u401 ic so8m1 mc100ept22d motorola mc100ept22d 39 1 u402 ic tssop20 mc100ep29dt on semiconductor mc100ep29dt 40 1 u403 ic so8m1 mc100ept23d motorola mc100ept23d 41 1 u501 ic sot23l5 nc7sz32m5, nc7sz32, tiny log uhs 2-input or gate fairchild nc7sz32m5 42 1 u502 ic tqfp128 cy7c68013 cypress cy7c68013-128axc or cy7c68014a-128axc 43 1 u503 ic dip8 24lc00p microchip 24lc00p 44 1 u504 ic dct_8pin_06, 5 mm sn74lvc2g74dctr, d-type flip-flop, dct_8pin_0.65mm texas instruments sn74lvc2g74dctr 45 1 u505 ic soic 14 74lvq04sc, low voltage hex inverter fairchild 74lvq04sc 46 1 u601 ic dip20/sol 74lcx574wm-nd, 74lcx574 octal d-type flip-flop fairchild 74lcx574wm-nd 47 1 vr301 ic sot-223hs high accuracy, adp3339akc-3.3, 3.3 v analog devices adp3339akc-3.3 48 1 y501 crystal crystal oscillator , 24 mhz ecliptek ec-12-24.000m 49 6 see schematic for placement connector 100 mil jumper 0.1 jumpers samtec snt-100-bk-g-h 50 4 insert from bottom side of board standoff plastic mount standoffs 7/8 height, standoffs richco cbsb-14-01a-rt 51 2 see schematic for placement connector third-row header key these header inserts for j104, pin 81, and pin 120 are located on the edges of the top row samtec tsw-104-07-t-s 1 only u201 is populated for the sing le-channel version (h sc-adc-evalb-sc).
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 25 of 28 ordering information ordering guide model description HSC-ADC-EVALB-SC single fifo version of usb evaluation kit hsc-adc-evalb-dc dual fifo version of usb evaluation kit hsc-adc-fpga-4/-8 quad/octal serial lvds to dual parallel cmos interfac e; supports all quad/octal adcs in this family except the ad9289 (not included in evaluation kit) hsc-adc-fpga-9289 quad serial lvds to dual parallel cmos inte rface for the ad9289 only (not included in evaluation kit) ad922xffa 1 adapter for ad922x family (not included in evaluation kit) ad9283ffa 1 adapter for the ad9283 and ad9057 (not included in evaluation kit) ad9059ffa 1 adapter for the ad9059 (not included in evaluation kit) ad9051ffa 1 adapter for the ad9051 (not included in evaluation kit) lg-0204a 1 adapter for the ad10xxx and ad13xxx families (not included in evaluation kit) 1 if an adapter is needed, send an e mail to highspeed.converters@analog.com. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 26 of 28 notes
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 27 of 28 notes
HSC-ADC-EVALB-SC/hsc-adc-evalb-dc rev. 0 | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. eb05870-0-2/06(0)

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